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rev: 1.01 11/2002 1/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs818dv18d-333/300/250/200 18mb 2x2b4v sigmaquad sram 200 mhz?333 mhz 2.5 v v dd 1.8 v and 1.5 v i/o 165-bump bga commercial temp industrial temp features ? simultaneous read and write sigmaquad? interface ? jedec-standard pinout and package ? dual doubledata rate interface ? echo clock outputs track data output drivers ? byte write controls sampled at data-in time ? burst of 4 read and write ? 2.5 v +100/?100 mv core power supply ? 1.5 v or 1.8 v hstl interface ? pipelined read operation ? fully coherent read and write pipelines ? zq mode pin for programm able output drive strength ? ieee 1149.1 jtag-compliant boundary scan ? 165-bump, 13 mm x 15 mm, 1 mm bump pitch bga package ? pin-compatible with future 36mb, 72mb, and 144mb devices sigmaram ? family overview gs818dv18 are built in compliance with the sigmaquad sram pinout standard for separate i/o synchronous srams. they are18,874,368-bit (18mb) srams. these are the first in a family of wide, very low voltage hstl i/o srams designed to operate at the speeds needed to implement ec onomical high performance networking systems. sigmaquad srams are offered in a number of configurations. some emulate and enhance other synchronous separate i/o srams. a higher performance sdr (single data rate) burst of 2 versionis also offered. the logical differences between the protocols employed by these rams hinge mainly on various combinations of address bursting, output data registering, and write cueing. along with the common i/o family of sigmarams, the sigmaquad family of srams allows a user to implement the in terface protocol best suited to the task at hand. clocking and addr essing schemes a 2x2b4sigmaquad sram is a synchronous device. it employs two input register clock inputs, k and k . k and k are independent single- ended clock inputs, not differential i nputs to a single differential clock input buffer. the device also allows the user to manipulate the output register clock inputs quasi independently with the c and c clock inputs. c and c are also independent singl e-ended clock inputs, not differential inputs. if the c clocks are tied high, the k clocks are routed internally to fire the output registers instead. each 2x2b4 igmaquad sram also supplies echo clock outputs, cq and cq , that are synchronized with read data out put. when used in a source synchronous clocking scheme, these echo clock outputs can be used to fire input registers at the data?s destination. because separate i/o 2x2b4 rams always transfer data in four packets, a0 and a1 are internally se t to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfers. because the lsbs are tied off in ternally, the address field of a 2x2b4 ram is always two address pins less than the advertised index depth (e.g., the 1m x 18 has a 256k addressable index). - 333 -300 -250 -200 tkhkh 3.0 ns 3.3 ns 4 ns 5 ns tkhqv 1.6 ns 1.8 ns 2.1 ns 2.3 ns 165-bump, 13 mm x 15 mm bga 1 mm bump pitch, 11 x 15 bump array bottom view jedec std. mo-216, variation cab-1
rev: 1.01 11/2002 2/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 1m x 18 sigmaquad sram ? top view 1234567891011 a cq mcl/sa (144mb) nc/sa (36mb) w bw1 k nc r sa mcl/sa (72mb) cq b nc q9 d9 sa nc k bw0 sa nc nc q8 c nc nc d10 v ss sa nc sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h nc v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss sa sa sa v ss nc nc d1 p nc nc q17 sa sa c sa sa nc d0 q0 r tdo tck sa sa sa c sa sa sa tms tdi 11 x 15 bump bga?13 x 15 mm2 body?1 mm bump pitch notes: 1. expansion addresses: a3 for 36mb, a10 for 72mb, a2 for 144mb 2. bw0 controls writes to d0:d8. bw1 controls writes to d9:d17. 3. mcl = must connect low 4. it is recommended that h1 be tied low for compatibility with future devices.
rev: 1.01 11/2002 3/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 note: nc = not connected to die or any other pin background separate i/o srams, from a system architec ture point of view, are attractive in app lications where alternating reads and writes are needed. therefore, the sigmaquad sram interface a nd truth table are optimized for alternati ng reads and writes. separate i/o srams are unpopular in applications where multiple reads or mult iple writes are needed because burst read or wr ite transfers from separate i/o srams c an cut the ram?s bandwidth in half. a sigmaquad sram can begin an alternating sequenc e of reads and writes with either a read or a write. in order for any separate i/o sram that shares a common address between its two ports to keep both ports running all the time, the ram must implement some sort of burs t transfer protocol. the burst must be at least long enough to cover the ti me the opposite port is receiving instructions on what to do ne xt. the rate at which a ram can accept a new random address is the most fundamental performance metric for t he ram. each of the three sigmaquad srams support similar address rates because random addr ess rate is determined by the internal performance of the ram and they are all based on the pin description table symbol description type comments sa synchronous address inputs input ? nc no connect ? ? r synchronous read input active low w synchronous write input active low bw0 ?bw1 synchronous byte writes input active low k input clock input active high k input clock input active low c output clock input active high c output clock input active low tms test mode select input ? tdi test data input input ? tck test clock input input ? tdo test data output output ? v ref hstl input reference voltage input ? zq output impedance matching input input ? mcl must connect low ? ? cq synchronous echo clock out put output echoes c or k clock cq synchronous echo clock-bar output output echoes c or k clock d0?d17 synchronous data inputs input ? q0?q17 synchronous data outputs output ? v dd power supply supply 2.5 v nominal v ddq isolated output buffer supply supply 1.5 v nominal v ss power supply: ground supply ?
rev: 1.01 11/2002 4/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 same internal circuits. differences between the truth tables of the different sigmaq uad srams, or any other separate i/o srams, follow from differences in how the ram?s interface is c ontrived to interact with the rest of the system. each mode of operation has its own advantages and disadvantages. the user should consider the nature of the work to be done by the ram to evaluate which version is best suited t o the application at hand. alternating read-write operations sigmaquad srams follow a few simple rules of operation. - read or write commands issued on one port are never allow ed to interrupt an operation in progress on the other port. - read or write data transfers in progres s may not be interrupted and re-started. - r and w high always deselects the ram but does not disable the cq or cq output pins. - all address, data, and control inputs are sampled on clock edges. in order to enforce these rules, each ram combines present st ate information with command inputs. see the truth table for detai ls.
rev: 1.01 11/2002 5/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 2x2b4 sigmaquad sram ddr read the status of the address input, w , and r pins are sampled at each rising edge of k. w and r high causes chip disable. a low on the read enable-bar pin, r , begins a read cycle. r is always ignored if the previous command loa ded was a read command. thefourresulting data output transfers begin after the next rising edge of the k clock. data is clocked out by the next rising edge of the c, the rising edg e of c after that, the next rising edge of c, and finally by the next rising edge of c . 2x2b4 double data rate si gmaquad sram read first dwg rev. g dc0 dc1 dc2 dc3 de0 qb0 qb1 qb2 qb3 qd0 /cq /w d q cq /bwx c /c de f /r address xx b c write read write read k /k no op read
rev: 1.01 11/2002 6/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 2x2b4 sigmaquad sram ddr write the status of the address input, w , and r pins are sampled at each rising edge of k. w and r high causes chip disable. a low on the write enable-bar pin, w , and a high on the read enable-bar pin, r , begins a write cycle. w is always ignored if the previous command was a write command. data is clocked in by the next rising edge of k, the rising edge of k after that, the next rising edge of k, and finally by the next rising edge of k . 2x2b4 double data rate si gmaquad sram write first special functions byte write control byte write enable pins are sampled at the same time that data in is sampled. a high on the byte write enable pin associated wit h a particular byte (e.g., bw0 controls d0?d8 inputs) will inhi bit the storage of that particular byte, leaving whatever data may be stored at the current ad dress at that byte location undisturbed. any or all of the byte writ e enable pins may be driven high or low during the data in sample times in a write sequence. dwg rev. g db0 db1 db2 db3 dd0 dd1 dd2 qc0 qc1 qc2 cq /cq de /w d q c /c /bwx f /r address xx b c read write read write k /k no op write
rev: 1.01 11/2002 7/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 each write enable command and write address l oaded into the ram provides the base addres s for a 4 beat data transfer. the x18 v ersion of the ram, for example, may write 72 bits in association with eac h address loaded. any 9-bit byte may be masked in any write sequence . example x18 ram write sequence using byte write enables resulting write operation output register control sigmaquad srams offer two mechanisms for controlling the output dat a registers. typically, control is handled by the output reg ister clock inputs, c and c . the output register clock inputs can be us ed to make small phase adjustments in the fi ring of the output registers by allowin g the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the k and k clocks. if the c and c clock inputs are tied high, the ram reverts to k and k control of the outputs, allowing the ram to function as a conventional pipelined read sram. echo clock sigmaquad srams feature echo clock outputs, cq and cq , that track the performance of the output drivers. the echo clocks are delayed copies of the output register clocks, c and c or k and k (if the c and c clock inputs are tied high). echo clo cks are designed to track changes in output driver delays due to variance in die temperature and s upply voltage. the echo clocks are designed to fire with the re st of the data output drivers. sigmaquad srams provide both in-phase, or true, echo clock output , cq and inverted echo clock output cq . echo clocks are always active. neither inhibiting reads via holding r high, nor deselection of the ram via holding r and w high will deactivate the echo clocks. data in sample time bw0 bw1 d0?d8 d9?d17 beat 1 0 1 data in don?t care beat 2 1 0 don?t care data in beat 3 0 0 data in data in beat 4 1 0 don?t care data in byte 1 d0?d8 byte 2 d9?d17 byte 3 d0?d8 byte 4 d9?d17 byte 5 d0?d8 byte 6 d9?d17 byte 7 d0?d8 byte 8 d9?d17 written unchanged unchanged written written written unchanged written
rev: 1.01 11/2002 8/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 example four bank dept h expansion schematic a k r w a 0 ?a n k w 0 d 1 ?d n bank 0 bank 1 bank 2 bank 3 r 0 cq d a k w cq d a k w cq d a k w cq d r r r qqq q cc cc q 1 ?q n c cq 0 cq 1 cq 2 cq 3 w 1 r 1 w 2 r 2 w 3 r 3 note: for simplicity bwn , k , c and cq are not shown.
rev: 1.01 11/2002 9/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 2x2b4 sigmaquad sram depth expansion dwg rev. g dc0 dc1 dc2 dc3 de0 de1 de2 de3 qd0 qd1 qd2 qd3 qb0 qb1 qb2 qb3 qb0 qb1 qb2 qb3 qd0 qd1 qd2 qd3 cq bank 1 c q bank 2 q bank 1 b /c cq bank 2 q bank 1 + q bank 2 /r2 /r1 /w1 /w2 d bank 1 d bank 2 g de f c address xx wri te - bank 2 bank 2 bank 1 bank 2 bank 1 bank 1 write read write read k /k no op read
rev: 1.01 11/2002 10/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 flxdrive-ii output driver impedance control hstl i/o sigmaquad srams are supplied wi th programmable impedance output drivers. the zq pin must be connected to v ss via an external resistor, rq, to allow the sram to monito r and adjust its output driver impedance. the va lue of rq must be 5x the value of the intended line impedance driven by the sram. the allowable range of rq to guarantee impedance matc hing with a vendor-specified tolerance is be tween 150 ? and 300 ? . periodic readjustment of the output driver impedance is necessa ry as the impedance is affected by drifts in supply voltage an d temperature. a clock cycle counter peri odically triggers an impedance evaluation, rese ts and counts again. each impedance evalu ation may move the output driver impedance level one step at a time towards the optimum level. the output dr iver is implemented with disc rete binary weighted impedance steps. impedance updates for ?0s? occur whenever the sram is driving ?1s? for t he same dqs (and vice-versa f or ?1s?) or the sram is in hi-z. the sram requires 32k st art-up cycles, selected or deselected, after v dd reaches its operating range to reach its programmed output driver impedance. separate i/o 2x2b4 sigmaquad s ram truth table ar w previous operation current operation ddddqqqq k (t n ) k (t n ) k (t n ) k (t n-1 ) k (t n ) k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) x 1 1 deselect deselect x x ? ? hi-z hi-z ? ? x 1 x write deselect d2 d3 ? ? hi-z hi-z ? ? x x 1 read deselect x x ? ? q2 q3 ? ? v 1 0 deselect write d0 d1 d2 d3 hi-z hi-z ? ? v 0 x deselect read x x ? ? q0 q1 q2 q3 vx0 read write d0d1d2 d3q2q3 ? ? v 0 x write read d2 d3 ? ? q0 q1 q2 q3 notes: 1. ?1? = input ?high?; ?0? = input ?low?; ?v? = input ?valid?; ?x? = input ?don?t care? 2. ??? indicates that the input re quirement or output state is determined by the next operation. 3. q0, q1, q2, and q3 indi cate the first, second, third, and fourth pieces of output data tr ansferred during read operations. 4. d0, d1, d2, and d3 indi cate the first, second, third, a nd fourth pieces of input data tr ansferred during write operations. 5. qs are tristated for one cycle in response to deselect a nd write commands, one cycle after the command is sampled, except when preceded by a read command. 6. cqs are never tristated. 7. users should not clock in metastable addresses.
rev: 1.01 11/2002 11/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 byte write clock truth table x18 byte write enable (bwn ) truth table bw bw bw bw current operation d d d d k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) k (t n ) k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) tttt write dx stored if bwn = 0 in all four data transfers d0 d2 d3 d4 tfff write dx stored if bwn = 0 in 1st data transfer only d0xxx ftff write dx stored if bwn = 0 in 2nd data transfer only xd1x x fftf write dx stored if bwn = 0 in 3rd data transfer only xxd2x ffft write dx stored if bwn = 0 in 4th data transfer only xxxd3 ffff write abort no dx stored in any of the four data transfers xxxx notes : 1. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?. 2. if one or more bwn = 0, then bw = ?t?, else bw = ?f?. bw0 bw1 d0?d8 d9?d17 1 1 don?t care don?t care 0 1 data in don?t care 1 0 don?t care data in 0 0 data in data in
rev: 1.01 11/2002 12/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 recommended oper ating conditions absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 3.6 v v ddq voltage in v ddq pins ?0.5 to 2.5 v v ref voltage in v ref pins ?0.5 to v ddq v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( 2.5 v max.) v v in voltage on other input pins ?0.5 to v ddq +0.5 ( 2.5 v max.) v i in input current on any pin +/?100 ma dc i out output current on any i/o pin +/?100 ma dc t j maximum junction temperature 125 o c t stg storage temperature ?55 to 125 o c note: permanent damage to the device may occur if the absolute maximu m ratings are exceeded. operati on should be restricted to recomm ended operating conditions. exposure to conditi ons exceeding the recommended operating condi tions, for an extended period of time, ma y affect reliability of this component. power supplies parameter symbol min. typ. max. unit notes supply voltage v dd 2.4 2.5 2.6 v 1.8 v i/o supply voltage v ddq 1.7 1.8 1.95 v 1 1.5 v i/o supply voltage v ddq 1.4 1.5 1.6 v 1 ambient temperature (commercial range versions) t a 02570 c2 ambient temperature (industrial range versions) t a ?40 25 85 c2 notes: 1. unless otherwise noted, all perfo rmance specifications quoted are evaluated for worst case at both 1.4 v v ddq 1.6 v (i.e., 1.5 v i/o) and 1.7 v v ddq 1.95 v (i.e., 1.8 v i/o) and quoted at whichever condition is worst case. 2. the power supplies need to be powered up simu ltaneously or in the following sequence: v dd , v ddq , v ref , followed by signal inputs. the power down sequence must be the reverse. v ddq must not exceed v dd . 3. most speed grades and configurations of this device are of fered in both commercial and industrial temperature ranges. the par t number of industrial temperature range versions end the character ?i?. unless otherwise noted, all per formance specifications quoted a re evaluated for worst case in the temperature range marked on the device.
rev: 1.01 11/2002 13/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 hstl i/o ac input definitions hstl i/o dc input characteristics parameter symbol min max units notes dc input logic high v ih (dc) v ref + 200 mv 1 dc input logic low v il (dc) v ref ? 200 mv 1 v ref dc voltage v ref (dc) v ddq (min)/2 v ddq (max)/2 v1 notes: 1. compatible with both 1.8 v and 1.5 v i/o drivers hstl i/o ac input characteristics parameter symbol min max units notes ac input logic high v ih (ac) v ref + 400 mv 3,4 ac input logic low v il (ac) v ref ? 400 mv 3,4 v ref peak to peak ac voltage v ref (ac) 5% v ref (dc) mv 1 notes: 1. the peak to peak ac co mponent superimposed on v ref may not exceed 5% of the dc component of v ref . 2. to guarantee ac characteristics, v ih ,v il , trise, and tfall of i nputs and clocks must be within 10% of each other. 3. for devices supplied with hstl i/o input buffers. compatible with both 1.8 v and 1.5 v i/o drivers. 4. see ac input definition drawing below. v ih (ac) v ref v il (ac)
rev: 1.01 11/2002 14/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 package thermal characteristics rating layer board symbol max unit notes junction to ambient (at 200 lfm) single r ja tbd c/w 1,2 junction to ambient (at 200 lfm) four r ja tbd c/w 1,2 junction to case (top) ? r jc tbd c/w 3 notes: 1. junction temperature is a function of sram power dissipatio n, package thermal resistance, mounting board temperature, ambient. temperature air flow, boar d density, and pcb thermal resistance. 2. scmi g-38-87 3. average thermal resistance between die a nd top surface, mil spec-883, method 1012.1 ac test conditions parameter conditions input high level v ddq input low level 0 v max. input slew rate 2 v/ns input reference level v ddq /2 output reference level v ddq /2 notes: test conditions as specified with output loading as shown unless otherwise noted. 20% tkhkh v ss ? 1.0 v 50% v ss v ih undershoot measurement and timing overshoot measurement and timing 20% tkhkh v dd + 1.0 v 50% v dd v il
rev: 1.01 11/2002 15/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 ac test load diagram input and output leakage characteristics parameter symbol test co nditions min. max notes input leakage current (except mode pins) i il v in = 0 to v dd ?2 ua 2 ua mode pin input current i inm v dd v in v il 0 v v in v il ?100 ua ?2 ua 2 ua 2 ua output leakage current i ol output disable, v out = 0 to v ddq ?2 ua 2 ua programmable impedance hstl output driver dc electrical characteristics parameter symbol min. max. units notes output high voltage v oh v ddq / 2 v ddq v 1,3 output low voltage v ol vss v ddq / 2 v 2,3 notes: 1. i oh = (v ddq /2) / (rq/5) +/? 15% @ v oh = v ddq /2 (for: 150 ? rq 300 ?). 2. i ol = (v ddq /2) / (rq/5) +/? 15% @ v ol = v ddq /2 (for: 150 ? rq 300 ?) . 3. parameter tested with rq = 250 ? and v ddq = 1.5 v or 1.8 v dq vt = v ddq /2 50 ? rq = 250 ? (hstl i/o)
rev: 1.01 11/2002 16/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 operating currents parameter org symbol -333 -300 -250 test conditions 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c operating current x18 idd 400 ma tbd ma 375 ma tbd ma 330 ma tbd ma r and w v il max. tkhkh tkhkh min. all other inputs v in v il max. or v in v ih min. iddq 95 ma tbd ma 85 ma tbd ma 70 ma tbd ma chip disable current x18 isb1 155 ma tbd ma 150 ma tbd ma 140 ma tbd ma r and w v ih min. tkhkh tkhkh min. all other inputs v in v il max. or v in v ih min. isbq1 5 ma tbd ma 5 ma tbd ma 5 ma tbd ma note: power measured with output pins floating.
rev: 1.01 11/2002 17/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 ac electrical characteristics parameter symbol -333 -300 -250 -200 units notes min max min max min max min max k, k clock cycle time c, c clock cycle time t khkh t chch 3.0 ? 3.3 ? 4.0 ? 5.0 ? ns k, k clock high pulse width c, c clock high pulse width t khkl t chcl 1.2 ? 1.3 ? 1.5 ? 2.0 ? ns k, k clock low pulse width c, c clock low pulse width t klkh t clch 1.2 ? 1.3 ? 1.5 ? 2.0 ? ns k clock high to k clock high c clock high to c clock high t khk h t chc h 1.3 ? 1.5 ? 1.8 2.2 ns 4 k clock high to k clock high c clock high to c clock high t k hkh t c hch 1.3 ? 1.5 ? 1.8 2.2 ns k, k clock high to c, c clock high t khch 0 1.3 0 1.45 0 1.8 0 2.3 ns address input setup time t avkh 0.4 ? 0.4 ? 0.5 ? 0.6 ? ns address input hold time t khax 0.4 ? 0.4 ? 0.5 ? 0.6 ? ns control input setup time t bvkh 0.4 ? 0.4 ? 0.5 ? 0.6 ? ns 1 control input hold time t khbx 0.4 ? 0.4 ? 0.5 ? 0.6 ? ns 1 data and byte write input setup time t dvkh 0.3 ? 0.3 ? 0.35 ? 0.4 ? ns data and byte write input hold time t khdx 0.3 ? 0.3 ? 0.35 ? 0.4 ? ns k, k clock high to data output valid c, c clock high to data output valid t khqv t chqv ? 1.6 ? 1.8 ? 2.1 ? 2.3 ns k, k clock high to data output hold c, c clock high to data output hold t khqx t chqx 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 2 k clock high to data output low-z c clock high to data output low-z t khqx1 t chqx1 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 2,3 k clock high to data output high-z c clock high to data output high-z t khqz t chqz 0.5 1.6 0.5 1.8 0.5 2.1 0.5 2.3 ns 2,3 k, k clock high to cq, cq clock high c, c clock high to cq, cq clock high t khcqh t chcqh 0.5 1.5 0.5 1.7 0.5 2.0 0.5 2.2 ns cq, cq clock high to data output valid t cqhqv ? 0.2 ? 0.2 ? 0.25 ? 0.3 ns 2 cq, cq clock high to data output hold t cqhqx ?0.2 ? ?0.2 ? ?0.25 ? ?0.3 ? ns 2
rev: 1.01 11/2002 18/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 cq, cq clock high pulse width t cqhcql t khkl 0.1 t khkl 0.1 t khkl 0.1 t khkl 0.1 ns 2 cq, cq clock low pulse width t cqlcqh t klkh 0.1 t klkh 0.1 t klkh 0.1 t klkh 0.1 ns 2 cq, cq clock high pulse width t cqhcql1 t chcl 0.1 t chcl 0.1 t chcl 0.1 t chcl 0.1 ns 2 cq, cq clock low pulse width t cqlcqh1 t clch 0.1 t clch 0.1 t clch 0.1 t clch 0.1 ns 2 notes: 1. these parameters apply to control inputs r and w . 2. these parameters are guaranteed by desi gn and characterizati on. not 100% tested. 3. these parameters are measured at 50mv from steady state voltage. 4. t khk h max is specified by t k hkh min. t chc h max is specified by t c hch min. parameter symbol -333 -300 -250 -200 units notes min max min max min max min max
rev: 1.01 11/2002 19/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 k and k controlled read-write-read timing diagram a4 a5 a6 k k a r q cq cq t khax t avkh t khbx t bvkh t khkh t khkl t klkh read write read deselect read write deselect write read write deselect a2 a3 w a7 d a8 a1 t khcqh t cqhcql t cqlcqh t khqx1 t khqz t khqv t khqx t cqhqx t cqhqv t khbx t bvkh bwn q10 q11 q12 q13 q30 q31 q40 q71 q32 q33 q41 q42 q43 q70 t khqv t khqx t cqhqx t cqhqv t khcqh d20 d21 d22 d23 t khdx t dvkh t khk h t k hkh t khdx t dvkh d50 d51 d52 d53 d60 d61 d62 d63 d80
rev: 1.01 11/2002 20/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 c and c controlled read-write-read timing diagram a4 a5 a6 k k a r read write read deselect read write deselect write read write deselect a2 a3 w a7 d a8 a1 bwn d20 d21 d22 d23 d50 d51 d52 d53 d60 d61 d62 d63 d80 q cq cq t chqx1 t chqz t chqv t chqx t cqhqx t cqhqv c c t khch q10 q11 q12 q13 q30 q31 q40 q32 q33 q41 q42 q43 q70 t chqv t chqx t cqhqx t cqhqv t khch t chcqh t cqhcql1 t cqlcqh1 t chcqh t chch t chcl t clch t chc h t c hch
rev: 1.01 11/2002 21/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 jtag port operation overview the jtag port on this ram operates in a manner that is co mpliant with ieee standard 1149.1-1990, a serial boundary scan interfa ce standard (commonly referred to as jtag). the jtag port input interface levels scale with v dd . the jtag output drivers are powered by v dd . disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain i nactive unles s clocked. tck, tdi, and tms are designed with internal pull-up circ uits.to assure normal operation of the ra m with the jtag port unused, tck, tdi, and tms may be left floating or tied to either v dd or v ss . tdo should be left unconnected. jtag port registers overview the various jtag registers, referred to as test access port or tap registers, are selected (one at a time) via the sequences of 1s and 0s applied to tms as tck is strobed. each of t he tap registers is a serial shift register that captures serial input data on the r ising edge of tck and pushes serial data out on the next falling edge of tck. when a register is selected, it is placed between the tdi and tdo p ins. instruction register the instruction register holds the instructi ons that are executed by the tap controller when it is moved into the run, test/idl e, or the various data register states. instructions are 3 bits long. the instruction register can be loaded when it is placed between the tdi an d tdo pins. the instruction register is automat ically preloaded with the idcode instruction at power-up or when ever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit regist er that can be placed between tdi and tdo. it allows serial test data to be passed th rough the ram?s jtag port to another device in the scan chain with as little delay as possible. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all i nputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input wi ll produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register pl aced between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controll er state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the falling edge of tck. this is the out put side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap rese t) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap contro ller is also reset autom atically at power-up.
rev: 1.01 11/2002 22/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pins. the flip flops are then daisy chained together so the levels found can be shifted seria lly out of the jtag port?s td o pin. the boundary scan regis ter also includes a number of place holder flip flops (always set to a logic 1). the relations hip between the device pins and the bits i n the boundary scan register is described in the sc an order table following. the boundary scan register , under the control of the tap controller, i s loaded with the contents of the rams i/o ring when the controller is in captur e-dr state and then is placed between the tdi and tdo pins when t he controller is moved to shift-dr state. sample-z, sample/preload and extest in structions can be used to acti vate the boundary scan register. jtag tap block diagram identification (id) register the id register is a 32-bit r egister that is loaded with a device and vendor s pecific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the code is loaded from a 32-bit on-chip rom. it describes various attri butes of the ram as indicated below. the register is then placed between the tdi and tdo pins when t he controller is moved into shift-dr sta te. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. tap controller instruction set overview there are two classes of instructions defined in the standar d 1149.1-1990; the standard (public) instructions, and device speci fic (private) instructions. some public instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. the tap on this device may be used to monitor all input and i/o pads, and can be used to load address, data or control si gnals into the ram or to preload the i/o buffers. when the tap controller is placed in capture-ir state the two l east significant bits of the in struction register are loaded wit h 01. when the controller is moved to the shift-ir state the instruction regi ster is placed between tdi and tdo. in this state the desired ins truction is serially loaded through the tdi input (while the previ ous contents are shifted out at tdo). for all instructions, the tap executes newly loaded instructions only when the controll er is moved to update-ir state. the tap instru ction set for this device is listed in the fol lowing table. instruction register id code register boundary scan register 0 1 2 0 1 2 31 30 29 0 1 2 n 0 bypass register tdi tdo tms tck test access port (tap) controller
rev: 1.01 11/2002 23/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register the bypass register is placed between tdi and tdo. this occur s when the tap controller is moved to the shift-dr state. this allo ws the board level scan path to be shortened to facilitate testing of other devices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public instruction. when the sample / preload instruction is loaded in the instru c- tion register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the bo undary scan register. boundary scan register locations are not associated with an input or i/o pin, and are loaded with the default state i dentified in the boundary scan chain table at the end of this section of the dat asheet. because the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring conten ts while the input buffers are in transition (i.e. in a metast able state). although allowing the tap to sample metastable inputs will not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture set- up plus hold time (tts plus tth). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan r egister. moving the controlle r to shift- dr state then places the boundary scan register between t he tdi and tdo pins. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruct ion register is loaded with al l logic 0s. the extest command does not block or override the ram?s input pins; ther efore, the ram?s internal state is still determined by its input pins. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 10 0 0 1 1 1 1
rev: 1.01 11/2002 24/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 typically, the boundary scan register is loaded with the desired pa ttern of data with the sample/preload command. then the exte st command is used to output the boundary scan register?s contents, in parallel, on the ram?s dat a output drivers on the falling e dge of tck when the controller is in the update-ir state. alternately, the boundary scan register may be loaded in parallel using the extest command. when the extest instruction is sele cted, the sate of all the ram?s input and i/o pins, as well as the defaul t values at scan register lo cations not associated with a pi n, are trans- ferred in parallel into the boundary scan register on the rising edge of tck in the capture-dr state, the ram?s output pins dri ve out the value of the boundary scan register location wi th which each output pin is associated. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in sh ift-dr mode. the idcode instruction is t he default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the instruction register , all ram outputs are forced to an inactive drive state (high- z) and the bound- ary scan register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. rfu these instructions are reserved for future use. in this device they replicate the bypass instruction. jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan register between tdi and tdo. 1 idcode 001 preloads id register and pl aces it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 rfu 011 do not use this instruction; reserved for future use. 1 sample/preload 100 captures i/o ring contents. plac es the boundary scan register between tdi and tdo. 1 rfu 101 do not use this instruction; reserved for future use. 1 rfu 110 do not use this instruction; reserved for future use. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state.
rev: 1.01 11/2002 25/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes test port input high voltage v ihj 0.6 * v dd v dd +0.3 v1 test port input low voltage v ilj ? 0.3 0.3 * v dd v1 tms, tck and tdi input leakage current i inhj ? 300 1 ua 2 tms, tck and tdi input leakage current i inlj ? 1 100 ua 3 tdo output leakage current i olj ? 11ua4 test port output high voltage v ohj v dd ? 400 mv ? v5, 6 test port output low voltage v olj ? 0.4 v 5, 7 test port output cmos high v ohjc v dd ? 100 mv ? v5, 8 test port output cmos low v oljc ? 100 mv v 5, 9 notes: 1. input under/overshoot voltage must be ? 2 v > vi < v dd +2 v not to exceed 2.6 v maximu m, with a pulse width not to exceed 20% ttkc. 2. v ilj v in v dd 3. 0 v v in v iljn 4. output disable, v out = 0 to v dd 5. the tdo output driver is served by the v dd supply. 6. i ohj = ? 4 ma 7. i olj = + 4 ma 8. i ohjc = ?100 ua 9. i ohjc = +100 ua notes: 1. distributed scope and test jig capacitance. 2. test conditions as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v dd input low level 0.2 v input slew rate 1 v/ns input reference level v dd /2 output reference level v dd /2 dq v t = v dd /2 50 ? 30pf * jtag port ac test load * distributed test jig capacitance
rev: 1.01 11/2002 26/26 specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi re presentative. preliminary gs818dv18d-333/300/250/200 jtag port timing diagram jtag port ac electrical characteristics ordering information?gsi sigmaquad sram parameter symbol min. max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 20 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 10 ? ns tdi & tms hold time tth 10 ? ns org part number 1 type package speed (mhz) t a 3 1m x 18 gs818 d v18d-333 sigmaquad sram 1 mm pitch, 165-pin bga 333 c 1m x 18 gs818 d v18d-300 sigmaquad sram 1 mm pitch, 165-pin bga 300 c 1m x 18 gs818 d v18d-250 sigmaquad sram 1 mm pitch, 165-pin bga 250 c 1m x 18 gs818 d v18d-333i sigmaquad sram 1 mm pitch, 165-pin bga 333 i 1m x 18 gs818 d v18d-300i sigmaquad sram 1 mm pitch, 165-pin bga 300 i 1m x 18 gs818 d v18d-250i sigmaquad sram 1 mm pitch, 165-pin bga 250 i notes: 1. customers requiring delivery in tape and reel should add th e character ?t? to the end of the part number. example: gs818x36d-300t. 2. t a = c = commercial temperature range. t a = i = industrial temperature range. ttkq tts tth ttkh ttkl tck tms tdi tdo ttkc

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